Serial Peripheral Interface Motorola
A SPI receiver is written in VHDL and implemented on a CPLD as a SPI slave device. This allows the CPLD to act as an output expander, turning two SPI lines and a chip select line into eight output lines (8 digital outputs).SPI (Serial Peripheral Interface) is a four-wire synchronous serial bus. In this example, only three wires are used (data, clock and chip select) as data is only being received by the VHDL SPI receiver from a microcontroller (the micro is the SPI master).This is the first example of microcontroller to CPLD interfacing on this VHDL course so far. The microcontroller was previously only used to generate a clock pulse for the CPLD.This video shows the hardware, microcontroller software and VHDL code for this tutorial in action.
Serial Peripheral Interface Using Vhdl Code
SPI-FPGA-VHDLSerial Peripheral Interface (SPI) is a synchronous serial data protocol used for communication between digital circuits. Therefore with SPI interface FPGAs or microcontrollers can communicate with peripheral devices, sensors and also other FPGAs and microcontrollers quickly over short distances.In this implementation both SPI master and SPI slave components are written in VHDL and can be used for all FPGAs.